SYSCTL_DC1_ADC1SPD=SYSCTL_DC1_ADC1SPD_125K, SYSCTL_DC1_ADC0SPD=SYSCTL_DC1_ADC0SPD_125K
Device Capabilities 1
| SYSCTL_DC1_JTAG | JTAG Present |
| SYSCTL_DC1_SWD | SWD Present |
| SYSCTL_DC1_SWO | SWO Trace Port Present |
| SYSCTL_DC1_WDT0 | Watchdog Timer 0 Present |
| SYSCTL_DC1_PLL | PLL Present |
| SYSCTL_DC1_TEMP | Temp Sensor Present |
| SYSCTL_DC1_HIB | Hibernation Module Present |
| SYSCTL_DC1_MPU | MPU Present |
| SYSCTL_DC1_ADC0SPD | Max ADC0 Speed 0 (SYSCTL_DC1_ADC0SPD_125K): 125K samples/second 1 (SYSCTL_DC1_ADC0SPD_250K): 250K samples/second 2 (SYSCTL_DC1_ADC0SPD_500K): 500K samples/second 3 (SYSCTL_DC1_ADC0SPD_1M): 1M samples/second |
| SYSCTL_DC1_ADC1SPD | Max ADC1 Speed 0 (SYSCTL_DC1_ADC1SPD_125K): 125K samples/second 1 (SYSCTL_DC1_ADC1SPD_250K): 250K samples/second 2 (SYSCTL_DC1_ADC1SPD_500K): 500K samples/second 3 (SYSCTL_DC1_ADC1SPD_1M): 1M samples/second |
| SYSCTL_DC1_MINSYSDIV | System Clock Divider 1 (SYSCTL_DC1_MINSYSDIV_100): Divide VCO (400MHZ) by 5 minimum 2 (SYSCTL_DC1_MINSYSDIV_66): Divide VCO (400MHZ) by 2*2 + 2 = 6 minimum 3 (SYSCTL_DC1_MINSYSDIV_50): Specifies a 50-MHz CPU clock with a PLL divider of 4 4 (SYSCTL_DC1_MINSYSDIV_40): Specifies a 40-MHz CPU clock with a PLL divider of 5 7 (SYSCTL_DC1_MINSYSDIV_25): Specifies a 25-MHz clock with a PLL divider of 8 9 (SYSCTL_DC1_MINSYSDIV_20): Specifies a 20-MHz clock with a PLL divider of 10 |
| SYSCTL_DC1_ADC0 | ADC Module 0 Present |
| SYSCTL_DC1_ADC1 | ADC Module 1 Present |
| SYSCTL_DC1_PWM0 | PWM Module 0 Present |
| SYSCTL_DC1_PWM1 | PWM Module 1 Present |
| SYSCTL_DC1_CAN0 | CAN Module 0 Present |
| SYSCTL_DC1_CAN1 | CAN Module 1 Present |
| SYSCTL_DC1_WDT1 | Watchdog Timer1 Present |